Frequency Multiplier with Delay Locked Loop -Based Clock Generator for System on Chip Applications

Kumar, G. Prasanna and Prabhakar, J. and Raju, Nagulancha (2021) Frequency Multiplier with Delay Locked Loop -Based Clock Generator for System on Chip Applications. In: Advanced Aspects of Engineering Research Vol. 4. B P International, pp. 123-131. ISBN 978-93-90888-06-1

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Any implementation of something like a specific form of the multiplier in automated frequency measurement systems depends primarily on the overall permitted variance of both the output frequency of that same transducer. Therefore, it will be usually best to always use frequency multipliers of that first category in transducers with such a slight variance. The suggested edge incorporates optimal speed and reliable activity that used an organizational structure as well as an unselected overlap. The suggested hybrid digital edge solution provides broadband with low-energy and low-area benefits as well as being a potential candidate for low-energy frequency summaries in deep CMOS sub-micrometer. A charge pump was substituted by a counter to integrate the automated interface. The overall system consists of all the resources for doing the operation of stable clock pulses for system on chip applications as well as the frequency multiplier. The frequency multiplying method is carried out how to use a clock amplification system based on an edge combiner, which is carried out using the C2MOS logic. Eventually, a computational review to verify the output is done. It is evident in contrast with other designs that this system absorbs less power than others do in the same phase.

Item Type: Book Section
Subjects: Eprint Open STM Press > Engineering
Depositing User: Unnamed user with email
Date Deposited: 18 Nov 2023 05:43
Last Modified: 18 Nov 2023 05:43

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